| Имя | Размер | Дата расшаривания | Контрольная сумма | Рейтинг | Длительность |
|---|---|---|---|---|---|
| SystemC | 10113735 | 2016-10-10 17:32:01 +00:00 … 2016-12-08 13:50:31 +00:00 | 8.6 | ||
| VHDL | 314513732 | 2016-10-10 17:32:01 +00:00 … 2016-12-11 15:25:26 +00:00 | 9.1 | ||
| Verilog | 76791734 | 2016-10-10 17:32:01 +00:00 … 2016-11-28 22:49:28 +00:00 | 8.6 | ||
| Verilog, System Verilog | 108977690 | 2016-10-10 17:32:01 +00:00 … 2016-12-08 19:56:24 +00:00 | 8.6 | ||
| Стешенко В.Примеры проектирования цифровых устройств с использованием языков описания аппаратуры | 427258 | 2016-10-10 17:32:01 +00:00 | 6.4 | ||
| ABEL-HDL reference manual.V8.0.pdf | 1630030 | 2016-11-04 10:49:12 +00:00 | JM35H64VCAEXCIYCH3VPL4PZOVI6KMJPBVDARAQ | ||
| Appendix B Counting and Shifting Circuit Techniques.pdf | 221197 | 2016-10-10 17:32:01 +00:00 | PZN2F3XRZO54WNAFEJ3YLEGH4PPV3BBS3M35WQQ | 8.0 | |
| Applications of Specification and Design Languages for SoCs (Vachoux).pdf | 6290696 | 2016-11-15 12:43:19 +00:00 | ON44ANLJMMW4PYAE5GYEK7TEWXA7BDQQRLVEYRA | 5.3 | |
| Case Study 1 - DC motor control.pdf | 353296 | 2016-10-10 17:32:01 +00:00 | LEH6JZO7BSIPTSVBEXL4FN2RB2KKZHVGKUEO6KA | 8.6 | |
| Case Study 2- Digital Filter Design.pdf | 246638 | 2016-10-10 17:32:01 +00:00 | 4Y32KG7FWBLU77X6U2LR63G6FR3TR4Z5BLAHJVA | 8.0 | |
| Chapter 1Introduction to Finite-State Machines and State Diagrams for the Design.pdf | 236890 | 2016-10-10 17:32:01 +00:00 | YRUGD3YX4LXE3J4DALGFMX2SRF2CUZL3MBXGTBA | 8.6 | |
| Chapter 2 Using State Diagrams to Control External Hardware Subsystems.pdf | 178530 | 2016-10-10 17:32:01 +00:00 | 7SA76OGZPRCF5PI2IMO3JWPA5SPBHOVXCIOJO2Y | 8.0 | |
| Chapter 3 Synthesizing Hardware from a State Diagram.pdf | 262450 | 2016-10-10 17:32:01 +00:00 | NCHIS5IEA2CV6H27CX6QWW32D5YABXLSHH64KDY | 8.0 | |
| Chapter 4 Synchronous Finite-State Machine Designs.pdf | 364357 | 2016-10-10 17:32:01 +00:00 | CJWQR2CAK6TFB4SMOXJEIWI77BVF4JUPRUCJF5I | 8.0 | |
| Chapter 5 The One Hot Technique in Finite-State Machine Design.pdf | 396230 | 2016-10-10 18:30:47 +00:00 | U2RJ44YGDOT2Y7ZZ2EKMXGYECDPTY6JP652QR4Y | 8.0 | |
| Chapter 8 Describing Combinational and Sequential Logic using Verilog HDL.pdf | 555216 | 2016-10-11 15:53:50 +00:00 | S6FHW2K5PSQ42DE6AQ5OYYTYTJM4L2CATZTO2VQ | 8.0 | |
| Chapter 9 Asynchronous Finite-State Machines.pdf | 383240 | 2016-10-10 17:32:01 +00:00 | HOP2A5IRVS2KWNQIORW6WBOY2EMWHADPMSQAKTI | 8.0 | |
| FSM design examples.pdf | 1721709 | 2016-10-14 13:58:52 +00:00 | IWA3XO76MI4CUYYFTDCMTGJJPS6BGLCI7HRZ2NA | 7.3 | |
| Introduction to VHDL.pdf | 617131 | 2016-10-11 15:53:50 +00:00 | A4XJNMKR2KZUJ4PJ6SPX7TKLT5T4CMGOSHL5SHA | 8.0 | |
| LED time multiplexing ckt, FIFO buffer, stop watch.pdf | 725344 | 2016-10-11 19:57:51 +00:00 | Z2D57FR7SNCLBBUH3KC66BOWF4OXIIIEM26J6AQ | 8.0 | |
| Morgan.Kaufmann.Systems.Engineering.with.SysML.UML.Feb.2008.pdf | 3641352 | 2016-12-05 22:56:34 +00:00 | UNKLTX734W465W7ZE6KUDN3KNXZUFXXGPRLIP7I | 5.3 | |
| ROM PLA and VHDL examples.pdf | 461123 | 2016-10-10 17:32:01 +00:00 | MGPZ3XO2P2Q77SLJX7QZJH72UFARAIMLLEIWYCY | 8.0 | |
| RTL methodology practice.pdf | 2799466 | 2016-11-06 19:04:27 +00:00 | DNA6C4S5OYTRL7EMCKZIE4QG43Y65UZVTADD2LA | 6.4 | |
| RTL methodology principles.pdf | 5258901 | 2016-10-31 18:14:47 +00:00 | SU7KCCLLNOBICQBZLAXEEPRFIJX3Y42UNJNE66Y | 5.3 | |
| Rashinkar P., Paterson P., Singh L. - System-on-a-Chip Verification- Methodology and Techniques (2001)(392s).pdf | 4491788 | 2016-11-27 17:00:05 +00:00 | 4GL522SSSPOQKYVZCQ7ONL6RMEXRAN2SWE5H4NQ | 3.7 | |
| Simulink, Matlab-to-VHDL Route for Full-Custom, FPGA Rapid Prototyping of DSP Algorithms.pdf | 197594 | 2016-10-10 17:32:01 +00:00 | 4R4BX76XGYOMIHWRJPCRMBXEEZ54VXEYQT77HKQ | 8.0 | |
| UART TX and RX sub systems.pdf | 1045622 | 2016-10-11 19:57:51 +00:00 | DZMMN2RNMJSFDXJNMFZD4KQSVTD2QHBYM3AC43Q | 7.3 | |
| VGA adapter.pdf | 492816 | 2016-10-10 17:32:01 +00:00 | BLACN33XRORGOVT5R6G3RFSONLLVYSVMLPPXMIQ | 8.0 | |
| VGA controller - graphical based.pdf | 1696291 | 2016-11-08 15:25:07 +00:00 | M5QTHUMVJ3MBQ226XCYGQHSS5XRDNO5MNDB4GVA | 5.3 | |
| VGA controller - text based.pdf | 1394686 | 2016-11-26 09:30:00 +00:00 | SRVMURRI5EPC4AWFPIQ75KYHWHZVTO56VNLPSFY | 6.4 | |
| VHDL Tutorial Solutions.pdf | 205615 | 2016-10-10 17:32:01 +00:00 | WLKZ5TH7PVFHTFAXRVBTFGT3XFOIDBXUCSSYFFQ | 8.0 | |
| clock synchronization.pdf | 4097747 | 2016-11-07 13:22:27 +00:00 | 25F3PS6YM6AP3NPGJVA6AWJHRPJWA6OOLXVJ7PA | 6.4 | |
| computer fundamentals.pdf | 559240 | 2016-10-11 17:55:47 +00:00 | ZXEHHPTWKYOM6AZQFJY3MY3WCVPMS37CWZWZRKQ | 8.0 | |
| counters and shift registers.pdf | 812420 | 2016-10-11 17:55:47 +00:00 | HRONSZQ7PWSUWVQ5FBZCB7HO6IRZH4SEG23MXBI | 8.0 | |
| design examples- floating pt adder,sign magnitude adder, hexa to 7 segment led.pdf | 712676 | 2016-10-11 19:57:51 +00:00 | KJBSYFBTWKQQWIMKFAI5DF6NNNB6GN2ITE55MAA | 8.0 | |
| design examples-shift register, binary counter, testbench.pdf | 444630 | 2016-10-10 17:32:01 +00:00 | KCZVFDCZYSUKNDAOOMQW7BHBCHIW2BMHFY4LPTA | 8.0 | |
| design of SAYEH processor - verilog.pdf | 833125 | 2016-10-11 19:57:51 +00:00 | 4QOJE3F3T5B7ZP342EF74QEYK2P4NVPI5CMZCVY | 8.0 | |
| design of counters and shift registers.pdf | 1022368 | 2016-10-11 17:55:47 +00:00 | JH4DGMP44RXFVJO7RIBDVXLJ4LXM6BET3MNYTTQ | 8.0 | |
| designing library components.pdf | 928959 | 2016-10-11 15:53:50 +00:00 | 75PILNCUZBQITLRBXA4YP7IAFDST66FCISGYB5I | 8.0 | |
| embedded basics,IOs,accelerators.pdf | 524026 | 2016-10-10 17:32:01 +00:00 | IGTETTERMZEGBOHYAWLPHTS2Y6YKVUH44DFSFHQ | 8.0 | |
| fibonacci , period counter,division ckt, accurate LF ckt.pdf | 676881 | 2016-10-11 15:53:50 +00:00 | YDEI3IF7VP3FITR6KHTWBKM4DOCUM543HIOWYHI | 8.0 | |
| flip-flops and related devies.pdf | 436357 | 2016-10-10 17:32:01 +00:00 | S2QEXF6CZ3FHYFVBKMFOCUY5UN27HGFQZXJYMUA | 8.0 | |
| fundamentals of digital logic with VHDL design solutions manual.pdf | 1787272 | 2016-12-08 13:50:31 +00:00 | TOFEXT33FFDDYA3Y575ELKICVMUPXFQR6DGMTIQ | 5.3 | |
| interfacing mouse with VHDL.pdf | 793522 | 2016-10-11 17:55:47 +00:00 | 5YBCLVC2OSKX54Q3YFX4WBWPH7FYSISTV5Y4JDY | 8.0 | |
| interfacing ps2 keyboard using VHDL.pdf | 794560 | 2016-10-11 15:53:50 +00:00 | AD7UYXBYKQYBZJJZRXSKENLA7JPQ6YQQKIX25UY | 8.0 | |
| introduction to digital filters.pdf | 668367 | 2016-10-11 15:53:50 +00:00 | Q2SI4GEEXMR4U57PVWLZUMKZDMSWSMMSUFQZTJI | 8.0 | |
| keyboard interface - verilog.pdf | 647295 | 2016-10-11 15:53:50 +00:00 | Z2S5UNZQP5VJTB5RDZQANS73QENFO6ZDJ2DF5ZY | 8.0 | |
| logic families and interfacing.pdf | 944320 | 2016-10-11 15:53:50 +00:00 | QZVBBE4GWM2O2HOQWONF6GGC624XP7OXDZUVZQI | 8.0 | |
| memories.pdf | 185186 | 2016-10-10 17:32:01 +00:00 | Z3NJEHD5RO4PRJCLVGNOK6E5PWIICHRFSBIFMLA | 8.6 | |
| memory devices - good.pdf | 382693 | 2016-10-10 17:32:01 +00:00 | 2ZCGQJMIMMCSESWS5BYIQEVKWA2QOJMYQKSVTDA | 8.0 | |
| numeric basics.pdf | 270125 | 2016-10-10 17:32:01 +00:00 | 4GB3QGWW7RLB6LIYSVKZKMWKSSQ4FYTVX7U4RLQ | 8.6 | |
| overview of fpga and EDA software.pdf | 1660368 | 2016-11-03 18:03:46 +00:00 | V7I3WN67FHIL6FCEAOITA27LQITCB7Z62RO6BPI | 6.4 | |
| rising edge detector, debounce ckt, testing ckt for that.pdf | 407757 | 2016-12-02 15:02:34 +00:00 | VQEBDHS6FNYCEVFPI2BGNDBK3SEH5QQHXIKFGLQ | 3.7 | |
| sequential basics.pdf | 294045 | 2016-10-10 17:32:01 +00:00 | H5OKLQLEKYQOMWZJRM7AVDU3S6PW4IT2QWEYOYQ | 8.0 | |
| sequential design principles.pdf | 2960093 | 2016-12-08 10:47:31 +00:00 | DDMQ3OWC3WB7M23TFCA5M2D26VV5YF653JK3GGY | 5.3 | |
| sequential multiplier.pdf | 651369 | 2016-10-11 15:53:50 +00:00 | SC3V5FUIU5MOWOY7BVJFJTXEZCOOJUOGKFZ46CY | 8.0 | |
| simple VHDL examples.pdf | 138118 | 2016-10-10 17:32:01 +00:00 | GZ3BACE3RV5RMVECNDMES45DAKUDNN54CKXSLCY | 8.6 | |
| spartan 3 specific memory and suggested experiments.pdf | 759204 | 2016-10-11 17:55:47 +00:00 | PAKZGT45GFXGFHKF7AYC77FFWICQLFNTCNJW5BA | 7.3 | |
| state machine design.pdf | 566930 | 2016-10-11 15:53:50 +00:00 | AT52NFGGWGNG6FUSVYY6VVMRRTYB3BRDWEMDABQ | 8.0 | |
| synthesis of VHDL code.pdf | 2988676 | 2016-11-17 22:21:49 +00:00 | FKZDD55IPU77LVPF5IRA5WYPKQX5II76C4R6NAI | 3.7 | |
| timing considerations.pdf | 1046702 | 2016-10-11 16:54:50 +00:00 | 7FAK2BHCSN2GWPZQWGDHBH7Z3MFGC7KOXBPWXPI | 8.0 | |
| vhdl and verilog user manual.PDF | 742157 | 2016-10-11 15:53:50 +00:00 | WXB4SCQ2F2I6NTO6D7FAXV5TOZDWAK5QXXNHCNQ | 6.4 | |
| writing test benches , test vectors, using text IO.pdf | 971695 | 2016-10-11 17:55:47 +00:00 | OX4HDV4EDSOZZVSCZRSI7QU3DE7RIMWPW6SIFMY | 8.0 | |
| Антонов А.П.Язык описаницифровых устройств AlteraHDL.Практический курс.2001.djvu | 2318719 | 2016-11-01 10:30:47 +00:00 | HGDUWJJVIOVKS5X3N3LKYMOTA7TOE22D5L2R4ZA | 5.3 | |
| Поляков А.К. Языки VHDL и Verilog в проектировании цифровой аппаратуры.djvu | 4931053 | 2016-11-03 12:58:46 +00:00 | PI2TKWGNU57RJALTXUU6GQ7L645XBSNHWPTLVTY | 6.4 | |
| Шпаргалка для перехода от AHDL к VHDL Статья Иосиф Каршенбойм и др (2003).pdf | 64542 | 2016-10-10 17:32:01 +00:00 | OX7T33DHRQZY6MHIAUUHRII7FK6B6DTXUNJDO6I | 8.0 | |
| Языки VHDL и VERILOG в проектировании цифровой аппаратуры (В.И. Поляков, 2003).pdf | 13848715 | 2016-11-01 07:27:47 +00:00 | 53FQOC36NV7D3XOVXY6CVUK6NNBTCETFTKZUT6I | ||
| Языки VHDL и VERILOG в проектировании цифровой аппаратуры (Поляков)(2003).djvu | 10624263 | 2016-10-25 18:44:52 +00:00 | 5EWIBKUBDBBGA5UOX46GVELEOGXABZQXVQQ3AOQ | 5.3 |