| Advanced Altera.pdf | 3983576 | 2016-11-24 19:54:58 +00:00 | YTAL5HXRIBR6H2NH73AYGIHYRXZJQEGPLZW4UEY | 6.1 | |
| Advanced Xilinx FPGA Design with ISE.PDF | 16705907 | 2016-11-25 07:04:50 +00:00 | SZZQWSC55GURHWYOPCRLFU3O2OSJC7YGK4UO5VA | 6.1 | |
| Altera-high speed design.pdf | 786585 | 2016-10-11 16:54:50 +00:00 | P4MZRCRODEVYB5L7AXV4G3MFPB4RIV5NENNCNNY | 8.4 | |
| An FPGA-Based Software Defined Radio Platform for the 2.4GHz ISM Band.pdf | 4581717 | 2016-11-15 16:45:23 +00:00 | ROVWHFOUMCJ5BWAOUXIDWNTGF3ZUSXOEYPS55LQ | 4.2 | |
| Architecture of FPGAs and CPLDs A Tutorial.pdf | 221548 | 2016-10-10 17:32:01 +00:00 | 6IFQD7Y3J3MC33SSDOZD4EKELZPKAOEUDDSIGWY | 8.4 | |
| Brown R.G.Getting started with programmable logic devices,the 16V8 and 20V8.2000.pdf | 118954 | 2016-10-10 17:32:01 +00:00 | TJRDMFNNFLCBPRQMSWABVHODCPTEPGMPJFNSNCA | 7.4 | |
| Digital Systems Design with FPGAs and CPLDs (Ian Grout).pdf | 9847956 | 2016-10-10 17:32:01 +00:00 | QFRZWKYLNLJSSZYHYC4Q3UTTKTC3D4HXBLILDYI | 6.1 | |
| FFT, Realization and Implementation in FPGA.pdf | 536775 | 2016-10-11 18:56:48 +00:00 | QRQ5BI6IGLOPOCOZVSRUB3ZZRC6P52SG4G5LCPI | 7.4 | |
| FPGA Configuration Guidelines.pdf | 59108 | 2016-10-10 17:32:01 +00:00 | GPUK2M5ZF6L4NAWWB2FYHGLD5TXSF32Q7CR626Y | 8.4 | |
| FPGA Design Tutorial.pdf | 2760761 | 2016-11-02 06:50:47 +00:00 | QJ3QRNMRHU5SEPPZQF3WURFP5PHFQ7ELU5XAZ7Y | 4.2 | |
| FPGA Routing Architecture.pdf | 115247 | 2016-10-10 17:32:01 +00:00 | RXTTPXQBCCIFTNMOTC5H5GU5FAUJU5BAVBDM35A | 7.4 | |
| FPGA implementation of a DSP core for full rate and half rate GSM vocoders.pdf | 305740 | 2016-10-10 17:32:01 +00:00 | YQBD5GDUDFLQF36ZV2TN353RXML67TPHDMDAPKI | 7.4 | |
| FPGA implementation of digital timing recovery in software radio receiver.pdf | 358591 | 2016-10-10 17:32:01 +00:00 | 5BLOHSVE5DVT6I2S5HTOQVA7ESQTB6TF2ZQINQI | 8.4 | |
| Fpga Qam Demodulator Design.pdf | 1551386 | 2016-12-03 08:41:52 +00:00 | IDJUBTXWBJBQG75J6HNQDGD6GBWWZUV7WA55PEQ | 4.2 | |
| Getting Started with FPGA tutorial.pdf | 782494 | 2016-10-11 15:53:50 +00:00 | 7EVRLGVPUTX4LCI7V3NCKWHNFG5JZVLQQHN3LJQ | 8.4 | |
| Good Manual Xilinx-Fpga Fpga Timing.pdf | 1033727 | 2016-10-11 15:53:50 +00:00 | XR43VR6JDNPLU7WIPV6UNVCN7Y2UNBZWEY7TKPY | 8.4 | |
| Guidelines For Designing High Speed Fpga Pcb.pdf | 5162000 | 2016-10-10 17:32:01 +00:00 | 7TOWLW5UE3YHEWARJPP7TYODB5ZV5A7BTFOT6OA | 7.4 | |
| Introduction To Cpld And Fpga Design_2.pdf | 1004754 | 2016-10-11 15:53:50 +00:00 | TWSPYJOQ4FL7ILWNER52Z7B6CGWV6D6VR2IE5NI | 8.4 | |
| Measuring the Gap between FPGAs and ASIC.pdf | 156658 | 2016-10-10 17:32:01 +00:00 | GEA52L2KUXOGH5PLCKQV5ELKAUE5MGM6SFLV4QY | 8.4 | |
| Memory, Microprocessor, and ASIC [Wai-Kai Chen 2003].pdf | 10136636 | 2016-11-07 23:30:24 +00:00 | LD6BW24AVE3N7DNWZUG2DRO4IXOTJUFHVPZPJVQ | 4.2 | |
| Newnes - Design Warriors Guide To Fpga.pdf | 4766815 | 2016-10-10 17:32:01 +00:00 | QDEPZ37SFBLNXHVQRPBHP64PLRRN73JJGU7HS7A | 7.4 | |
| Omondi A. R., Rajapakse J. C. (Ed) - FPGA Implementations of Neural Networks(2006)(First Edition)(368).pdf | 4285778 | 2016-11-13 07:57:52 +00:00 | PLBZ5TP72FR3BL2J2KAPEX3XG57SB3LJVK4GH6A | 4.2 | |
| Pellerin_D.,_Thibault_S._Practical_FPGA_Programming_in_C_(2005)(en)(464s).chm | 18207981 | 2016-12-05 03:39:26 +00:00 | J2VHLXV6KKVI5CIECM3MZMYLSYMMIKR7MJBXU2Y | 4.2 | |
| Rapid Prototyping of Digital Systems. A tutorial Approach (James Hamblen, Michael Furman).pdf | 22096093 | 2016-10-30 18:51:57 +00:00 | Y4JNI3U46NFM6BXH2M7AXEBGUW3JHZ6XF6RBGYY | 4.2 | |
| Sintez_na_PLIS_slojnih_shem.pdf | 358126 | 2016-10-10 17:32:01 +00:00 | 6N4KB4MPLO7IUNFBRTSAI4BDMEIQSB5SAOXL4RQ | 6.1 | |
| Zeidman_B._Introduction_to_CPLD_and_FPGA_Design(en)(40s).pdf | 1032689 | 2016-10-11 17:55:47 +00:00 | 2AUQVXCF3TZ6U5ASHYTZFXYQFN46N36R2F64JVY | 8.4 | |
| [Зотов]_Проектирование цифровых устройств на основе ПЛИС фирмы XILINX в САПР WebPack ISE_Ч2_2003.djvu | 9651705 | 2016-10-25 16:42:52 +00:00 | 6KHYCQ65CEOZGQOJK4MBUDN3XIEHBVEUU4QUGKY | 8.4 | |
| fpga_cpld_tut.pdf | 292267 | 2016-10-10 17:32:01 +00:00 | KV3HBMLXZ5O6T7DGCOSQD6RGDAYTQOR5XC6BM7A | 7.4 | |
| grush_plis1.djvu | 3950973 | 2016-10-19 15:21:55 +00:00 | UDBBB4SLERQHCSLC2ZWLDDAGMFAPZVRCQJWHOJQ | 6.1 | |
| virtex_rus.pdf | 1028676 | 2016-10-11 19:57:51 +00:00 | YVN3KRDEVC4BD2VZNF7PYJP4CLEFEAOIJA55ISI | 7.4 | |
| Антонов А.П. - Обзор элементной базы фирмы АЛьТЕРА.djvu | 2225243 | 2016-10-25 16:42:52 +00:00 | RBAFMIANKQ7VHUQDR5HZS7NJLYTAOUVKADT44XY | 4.2 | |
| Зотов В.Ю.Проектирование цифровых устройств на основе ПЛИС фириы XILINX в САПР WebPACK ISE.2003.djvu | 6702062 | 2016-11-11 16:50:43 +00:00 | 2X7TUAECD225DEB3NTPUTBMYJO27N4BEPGXXOHI | | |
| Комолов Д. А. - Системы автоматизированного проектирования фирмы Altera MAX+plus II и Quartus II. Краткое описание и самоучитель 2002.djvu | 13800174 | 2016-11-21 04:01:53 +00:00 | AAA537K5FUJKIOPDYNANRBY5XRLYUM3MZ2YYESI | 4.2 | |
| Максфилд Е. - Проектирование на ПЛИС. Курс молодого бойца - Додэка XXI (2007)(0-7506-7604-3)(DJVU) Русский, 978-5-94120-147-1.djvu | 9503510 | 2016-11-05 08:14:52 +00:00 | IAP7YUCUVPXWFVVQ7CCGN4GXKPI5JU4CVSYSNSA | 6.1 | |
| Максфилд К. Проектирование на ПЛИС. Архитектура, средства и методы 2007.djvu | 12291746 | 2016-10-12 09:10:53 +00:00 | JMRS6GSDT47S7BKLBBHYMWE65R5LJCROAHPFZEY | 4.2 | |
| П.П.Мальцев, Н.И.Гарбузов, А.П.Шарапов, Программируемые логические ИМС на КМОП-структурах и их применение - Энергоатомиздат (1998).djvu | 3889654 | 2016-10-14 22:05:52 +00:00 | 6HZGYBILBBDNXLK5UACFN7FXQFZOJKIXJQHJIEA | 4.2 | |
| ПЛИС VHDL пособие.pdf | 769536 | 2016-10-11 15:53:50 +00:00 | OL3UN3G2O4CZBRQUIBMBSG46H7H5SUBYRWLTFNY | 8.4 | |
| ПЛИС фирмы ALTERA. Проектирование устройств обработки сигналов (Стешенко)(2000).djvu | 3637556 | 2016-10-24 11:13:52 +00:00 | 53C6U5BSOHKE6EXUWUQ24P2EJVNMBSM54A65QRA | 4.2 | |
| ПЛИС фирмы Altera. Элементная база, система проектирования и язык описания аппаратуры В.Б.Стешенко (2007).pdf | 3732238 | 2016-12-03 16:57:45 +00:00 | MUT2S73XL4UGRJZAU725LOTDJDI6KV2266QM22Y | 4.2 | |
| Проектирование на ПЛИС. Курс молодого бойца (К. Максфилд, 2007).djvu | 12296731 | 2016-11-21 11:08:53 +00:00 | LTL7NXCRWYJTACZYW332BSNZNGY6MEX3IT5CEFI | | |
| Стешенко В.Б. - ПЛИС фирмы ALTERA[c] проектирование устройств обработки сигналов (2000)(ru).djvu | 3637556 | 2016-12-10 19:06:29 +00:00 | XZGMCB6I6NSNCH374NF6WSKSIZATSCPOU2SZGAY | | |